A Framework for Formal Verification of DRAM Controllers

The large number of recent JEDEC DRAM standard releases and their increasing feature set makes it difficult for designers to rapidly upgrade the memory controller IPs to each new standard. Especially the hardware verification is challenging due to the higher protocol complexity of standards like DDR5, LPDDR5 or HBM3 in comparison with their predecessors. With traditional simulation-based verification it is laborious to guarantee the coverage of all possible states, especially for control flow rich memory controllers. This has a direct impact on the time-to-market. A promising alternative is formal verification because it allows to ensure protocol compliance based on mathematical proofs. However, with regard to memory controllers no fully-automated verification process has been presented in the state-of-the-art yet, which means there is still a potential risk of human error. In this paper we present a framework that automatically generates SystemVerilog Assertions for a DRAM protocol. In addition, we show how the framework can be used efficiently for different tasks of memory controller development.Comment: ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022

Resource Centric Analysis of RSA and ECC Algorithms on FPGA

The electronics industry’s shadow side is counterfeiting, and the doom is growing. Almost every business in the supply chain is impacted by the issue, including component suppliers, distributors, Electronics Manufacturing Services (EMS) providers, Original Design Manufacturers (ODMs), Original Equipment Manufacturers (OEMs), and their clients. In fact, any electronics firm that wishes to benefit from the cheap costs associated with globalization must be aware that someone along the supply chain may be persuaded to acquire fake items and sell them as genuine. A thorough grasp of chip designs, including partitioning and prioritizing data transit and storage, as well as a range of obfuscation techniques and activity monitoring, is necessary to reduce the danger of future hardware breaches. To battle this problem, we need to enforce various security measures at different levels of the supply chain. The recent methods include implementing cryptographic ciphers into the devices. The commonly used ciphers are the hard ciphers. But owing to the advancements and increase in the number of low power and resource constrained devices, there has been a dire need to design ciphers that support such devices. This paper talks about the advantages of lightweight ciphers, aiming to secure low power devices and other embedded devices. This work mainly compares two algorithms, RSA(hard cipher) and ECC(light cipher) in terms of their device utilization and power consumption on a Kintex-7. The presented results are justified from simulations performed on the Vivado design suite

The Role of Memories in Transprecision Computing

Computing paradigms largely evolved over the last decades mainly driven by continuously increasing performance requirements, energy efficiency and power density challenges. Heterogeneous highly parallel architectures enhanced with dedicated accelerators tuned to specific applications, near-threshold computing, and recently approximate computing are examples of these new approaches. In this context the memory part was relatively untouched. However, memories play a central role in any computing system, are a major source of power consumption, and limit in many applications the overall compute performance. In this paper, we focus mainly on Dynamic Random Access Memories (DRAMs), which are today's most prominent external memories. In transprecision computing we address the DRAM memory challenge by several new approaches that are strongly related to the new techniques known on the compute side. In particular, these are the concept of approximate DRAM, advanced power-down modes and the integration of application knowledge into the memory system

Improving the error behavior of DRAM by exploiting its Z-channel property

In this paper, we present a new communication theoretic channel model for Dynamic Random Access Memory (DRAM) retention errors, that relies on the fully asymmetric retention error behavior of DRAM cells. This new model shows that the traditional approach is over pessimistic and we confirm this with real measurements of DDR3 and DDR4 DRAM devices. Together with an exploitation of the vendor specific true- and anti-cell structure, a low complexity bit-flipping approach is presented, that can largely increase DRAM's reliability with minimum overhead

An In-DRAM Neural Network Processing Engine

Many advanced neural network inference engines are bounded by the available memory bandwidth. The conventional approach to address this issue is to employ high bandwidth memory devices or to adapt data compression techniques (reduced precision, sparse weight matrices). Alternatively, an emerging approach to bridge the memory-computation gap and to exploit extreme data parallelism is Processing in Memory (PIM). The close proximity of the computation units to the memory cells reduces the amount of external data transactions and it increases the overall energy efficiency of the memory system. In this work, we present a novel PIM based Binary Weighted Network (BWN) inference accelerator design that is inline with the commodity Dynamic Random Access Memory (DRAM) design and process. In order to exploit data parallelism and minimize energy, the proposed architecture integrates the basic BWN computation units at the output of the Primary Sense Amplifiers (PSAs) and the rest of the substantial logic near the Secondary Sense Amplifiers (SSAs). The power and area values are obtained at sub-array (SA) level using exhaustive circuit level simulations and full-custom layout. The proposed architecture results in an area overhead of 25 % compared to a commodity 8 Gb DRAM and delivers a throughput of 63.59 FPS (Frames per Second) for AlexNet. We also demonstrate that our architecture is extremely energy efficient, 7.25× higher FPS/W, as compared to previous works

Fast validation of DRAM protocols with timed petri nets

In recent years, an increasing number of different JEDEC memory standards, like DDR4/5, LPDDR4/5, GDDR6, Wide I/O2, HBM2, and NVDIMM-P have been specified, which differ significantly from the previous ones like DDR3 and LPDDR3. Since each new standard comes with significant changes in the DRAM protocol compared to the previous ones, the developers of memory controllers and memory simulation models regularly face challenges implementing and verifying these new standards. In order to keep pace with these frequent changes of the requirements and the large variety of variants a robust validation methodology must be established. The JEDEC standards describe the complex memory protocol, i.e., DRAM commands and their timing dependencies, by using a mixture of state machine diagrams, tables, and timing diagrams. However, there exists no unique formal description of the JEDEC standards which could be used for a fast simulation-based validation. In this paper, for the first time, we present a comprehensive and formal mathematical model based on Petri Nets that contains the DRAM states, transitions, and timings. Furthermore, we present a Domain Specific Language (DSL) for describing the memory functionality and timing dependencies of a JEDEC standard in just a few lines of code. From this DSL description an executable Petri Net is generated automatically, which is used for the fast simulation-based validation of memory controllers and DRAM simulation models